Labs

Lab Assignments

• Lab 0: Getting Started
• Lab 1: Multiplexers and Adders (Due: September 16)
• Lab 2: Multipliers (Due: September 26)
• Lab 3: FFT Pipeline (Due: October 5)
• Lab 4: N-Element FIFOs (Due: October 12)
• Lab 5: RISC-V Introduction - Multi-cycle and Two-Stage Pipelines (Due: October 24)
• Lab 6: RISC-V Processor with 6-Stage Pipeline and Branch Prediction (Due: November 7)
• Lab 7: RISC-V Processor with DRAM and Caches (Due: November 18)
• Lab 8: RISC-V Processor with Exceptions (Due: November 25)

Project

• Part 1: Store Queue (Due: December 14)
• Part 2: Cache Coherence (Due: December 14)