Monday |
Wednesday |
Friday |
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Feb 3 - L01
Introduction
Take Self-Assessment Test!
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Feb 5 - Tutorial Session
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Feb 8 - L02
Hardwired, Single-cycle ISA Implementation
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Feb 10 - L03
Cache Organization
Self-Assessment Test DUE
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Feb 12 - Tutorial Session
Lab 0 DUE
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Tuesday Feb 16* - L04
Memory Management: From Absolute Addresses to Demand Paging
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Feb 17 - L05
Modern Virtual Memory
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Feb 19 - Tutorial Session
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Feb 22 - L06
Instruction Pipelining and Hazards
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Feb 24 - L07
Instruction Pipelining: Hazard Resolution and Timing Constraints
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Feb 26 - Tutorial Session
Lab 1 DUE
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Feb 29 - L08
Complex Pipelining: Superscalar and Scoreboarding
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Mar 2 - L09
Out of Order Execution and Register Renaming
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Mar 4 - Quiz 1
Up to L08
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Mar 7 - L10
Branch Prediction
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Mar 9 - L11
Speculative Execution and Recovery
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Mar 11 - Tutorial Session
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Mar 14 - L12
Advanced Memory Operations
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Mar 16 - L13
Reliability
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Mar 18 - Tutorial Session
Lab 2 DUE
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Mar 21 - SPRING BREAK
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Mar 23 - SPRING BREAK
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Mar 25 - SPRING BREAK
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Mar 28 - L14
Multithreading
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Mar 30 - L15
Cache Coherence (I)
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Apr 1 - Quiz 2
Up to L14
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Apr 4 - L16
Cache Coherence (II)
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Apr 6 - L17
Memory Consistency Models
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Apr 8 - Tutorial Session
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Apr 11 - L18
On-chip Networking (I)
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Apr 13 - L19
On-chip Networking (II)
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Apr 15 - Tutorial Session
Lab 3 DUE
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Apr 18 - Patriots' Day
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Apr 20 - L20
VLIW
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Apr 22 - Quiz 3
Up to L19
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Apr 25 - L21
SIMD and Vector Processors
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Apr 27 - L22
GPU Architectures
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May 1 - Tutorial Session
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May 2 - L23
Transactional Memory
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May 4 - L24
Virtualization
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May 6 - Tutorial Session
Lab 4 DUE
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May 9 - L25
Future Trends
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May 11 - Quiz 4
(In class)
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* - Monday, Feb 15th is President's day. Class is moved to Tuesday.