// 2-to-4 demultiplexer with active-low outputs 
// structural model
module demux1(a,b,enable,z);
  input a,b,enable;
  output [3:0] z;

  wire abar,bbar;	// local signals

  not v0(abar,a), v1(bbar,b);
  nand n0(z[0],enable,abar,bbar);
  nand n1(z[1],enable,a,bbar);
  nand n2(z[2],enable,abar,b);
  nand n3(z[3],enable,a,b);
endmodule


// 2-to-4 demultiplexer with active-low outputs
// dataflow model
module demux2(a,b,enable,z);
  input a,b,enable;
  output [3:0] z;

  assign z[0] = | {~enable,a,b};
  assign z[1] = ~(enable & a & ~b);
  assign z[2] = ~(enable & ~a & b);
  assign z[3] = enable ? ~(a & b) : 1'b1;
endmodule


// 2-to-4 demultiplexer with active-low outputs
// behavioral model
module demux3(a,b,enable,z);
  input a,b,enable;
  output [3:0] z;

  reg z;     // not really a register!

  always @(a or b or enable)
    case ({enable,a,b})
     default: z = 4'b1111;
     3'b100:  z = 4'b1110;
     3'b110:  z = 4'b1101;
     3'b101:  z = 4'b1011;
     3'b111:  z = 4'b0111;
    endcase
endmodule


module main;
  reg a,b,enable;
  wire [3:0] s_z,d_z,b_z;

  demux1 structural(a,b,enable,s_z);
  demux2 dataflow(a,b,enable,d_z);
  demux3 behavioral(a,b,enable,b_z);

  initial begin
    $dumpfile("demux.vcd"); $dumpvars(1,main);
 
    enable = 0; a = 0; b = 0;
    #10 enable = 1;
    #10 a = 1;
    #10 a = 0; b = 1;
    #10 a = 1;
    #10 enable = 0;
    $finish;
  end
endmodule