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IMPORTANT NOTE: The IAPBlue course was based on what we now call Bluespec Classic, which is a version that pre-dated the commercial offerings of Bluespec and is no longer available. To learn more about current Bluespec, please visit http://csg.csail.mit.edu/6.375/ or www.bluespec.com.

IAPBLUE 2003 Schedule

** Coffee will be available at 9:45 AM **

Monday, January 13th

10:00 - 10:55 AM - Lecture 1: Introduction

  • A new semantic model for hardware description and synthesis based on TRS
  • State and atomic actions
  • Two small examples
  • Lecture notes (PDF)

11:05 - 12:00 AM - Lecture 2: Compilation

  • Bluespec as a two-level language
  • Phase 1 — Generating the TRS
  • Phase 2 — Scheduling of operations
  • Lecture notes (PDF)

1:30 - 4:00 PM - Lab 1: TRS and rule scheduling

  • Understanding rule scheduling by analyzing Bluespec compiler output
  • Lab How-To handout (PS, PDF)
  • Lab Exercises handout (PS, PDF)
  • Lab source files (TAR)

Tuesday, January 14th

10:00 - 10:55 AM - Lecture 3: Introduction to Bluespec programming

  • Barrel shifter
  • Modules and instantiation
  • Parameterized barrel shifter
  • Lecture notes (PDF)

11:05 - 12:00 AM - Lecture 4: Example: IP Look up

  • Synchronous vs Asynchronous memory accesses
  • A pipelined architecture to keep the memory highly utilized
  • Conflicting rules and priorities
  • Lecture notes (PDF)

1:30 - 4:00 PM - Lab 2: FIFO

  • Write variations on a FIFO in Bluespec and analyze their operation
  • Lab Exercises handout (PS, PDF)
  • Lab source files (TAR)
  • Shifter source files (TGZ)
  • IP Lookup source files (TGZ)

Wednesday, January 15th

10:00 - 10:55 AM - Lecture 5: Example: Instruction decoding of MIPS

  • Instruction sets as an algebraic type
  • Type classes and Bits class
  • Pack & Unpack
  • Lecture notes (PDF)

11:05 - 12:00 AM - Lecture 6: Example: Instruction Pipelining

  • Development of 5-stage pipeline
  • Issues in encoding bypassing
  • Correctness issues
  • Lecture notes (PDF)

1:30 - 4:00 PM - Lab 3: Instruction Decoding

  • Write an alternate instruction decoder
  • Add simple processor pipeline variations
  • Lab Exercises handout (PS, PDF)
  • Lab source files (TAR)

Thursday, January 16th

10:00 - 10:55 AM - Lecture 7: Example: Out-of-order processor pipeline

  • Issues in modeling complex hardware operations
  • Reorder buffer and renaming
  • Branch prediction and speculative execution
  • Lecture notes (PDF)

11:05 - 12:00 AM - Lecture 8: Advanced topics (Guest lecturer - R.S. Nikhil, Sandburst)

  • Connectables
  • Multiple clock domains
  • Making registers accessible to the PCI Interface
  • Lecture notes (PDF)

1:30 - 4:00 PM - Lab 4: Processor Pipeline

  • Complete a 5-stage processor pipeline, expressing part of the design using Connectables
  • Lab Exercises handout (PS, PDF)