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Hardware Synthesis

We propose a novel high-level hardware design flow that will facilitate architectural exploration and dramatically reduce hardware design time. The design flow is based on a formalism known as Term Rewriting System (TRS). The central idea is to raise the level of hardware design abstractions and to make greater use of automated synthesis and verification tools. We seek not only to reduce the amount of tedium experts face in designing systems, but also to provide tools to assist novice designers.

Interesting Points

In our proposed TRS-based high-level architectural design flow, a hardware designer would spend the majority of his or her time and effort in producing and debugging a high-level architectural specification. The debugging will be interactive and at a high level of abstraction using automatically generated simulators and computer-aided proof systems. From a known-to-be-correct specification, multiple revisions of TRS descriptions containing various performance optimizations can be quickly generated both automatically and semiautomatically under human direction. The correctness of the optimized descriptions may follow by construction or may be checked against the initial architectural specification using computer aided verification. This will avoid a lengthy "hit-and-miss" validation process. The designer may iterate the process using tools designed to provide feedback regarding power, area and other metrics of interest. Finally the designer may select a design for more detailed synthesis. The potential reduction in time, effort and risk will enable hardware solutions to become competitive in many embedded applications, where currently software-on-DSP's is used as an engineering compromise.

Approach

We are developing the tool set necessary to realize this design flow. The major areas of work in our proposed design flow include:
  • Design capture in a TRS-based language

  • Computer-Assisted Design Methodology

  • Source-to-source architectural transformation

  • Formal design verification of source transformations

  • Automatically generated simulators with instrumentation

  • Feedback-driven architecture exploration

  • Automatic hardware synthesis.
Projects

Architecture
Malleable Caches
Commit-Reconcile and Fences(CRF)
Old CAA Projects

Computer-Aided Devices
Hardware Synthesis

Programming Languages
pH (Parallel Haskell)
Eager-Haskell
Implicit Parallel Programming in pH

Security
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