Monday |
Wednesday |
Friday |
Sep 02
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Sep 04 - L01
Introduction
Take Self-Assessment Test!
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Sep 06 - Tutorial Session
Hardwired, Single-cycle ISA Implementation
Self-Assessment Test DUE
|
Sep 9 - L02
Instruction Set Architectures and Cache Organization
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Sep 11 - L03
Memory Management: From Absolute Addresses to Demand Paging
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Sep 13 - Tutorial Session
Instruction Pipelining
Lab 1 Out
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Sep 16 - L04
Modern Virtual Memory
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Sep 18 - L05
Instruction Pipelining: Hazard Resolution and Timing Constraints
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Sep 20 - Holiday
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Sep 23 - L06
Complex Pipelining: Superscalar and Scoreboarding
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Sep 25 - L07
Out of Order Execution and Register Renaming
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Sep 27 - Tutorial Session
Lab 1 DUE
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Sep 30 - L08
Branch Prediction
Lab 2 Out
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Oct 2 - L09
Speculative Execution and Recovery
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Oct 4 - Tutorial Session
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Oct 7 - L10
Advanced Memory Operations
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Oct 9 - L11
Multithreading
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Oct 11 - Quiz 1
Up to L09
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Oct 14 - Holiday
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Oct 16 - L12
Cache Coherence (I)
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Oct 18 - Tutorial Session
Lab 2 DUE
Lab 3 Out
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Oct 21 - L13
Cache Coherence (II)
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Oct 23 - L14
Memory Consistency Models
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Oct 25 - Tutorial Session
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Oct 28 - L15
On-chip Networking (I)
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Oct 30 - L16
On-chip Networking (II)
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Nov 1 - Tutorial Session
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Nov 4 - L17
Transactional Memory
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Nov 6 - L18
VLIW
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Nov 8 - Quiz 2
Up to L16
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Nov 11 - Holiday
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Nov 13 - L19
Reliability
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Nov 15 - Tutorial Session
Lab 3 DUE
Lab 4 Out
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Nov 18 - L20
SIMD and Vector Processors
|
Nov 20 - L21
GPU Architectures
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Nov 22 - Tutorial Session
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Nov 25 - L22
Security
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Nov 27 - Holiday
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Nov 29 - Holiday
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Dec 2 - L23
Accelerators (I)
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Dec 4 - L24
Accelerators (II)
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Dec 6 - Tutorial Session
Lab 4 DUE
|
Dec 9 - L25
Future Trends
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Dec 11 - Quiz 3
(In class) Up to L24
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