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Wednesday |
Friday |
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Sep 05
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Sep 06 - L01
Introduction
Take Self-Assessment Test!
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Sep 08 - Tutorial Session
Hardwired, Single-cycle ISA Implementation
Self-Assessment Test DUE
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Sep 11 - L02
Instruction Set Architectures and Cache Organization
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Sep 13 - L03
Memory Management: From Absolute Addresses to Demand Paging
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Sep 15 - Tutorial Session
Instruction Pipelining
Lab 1 Out
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Sep 18 - L04
Modern Virtual Memory
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Sep 20 - L05
Instruction Pipelining: Hazard Resolution and Timing Constraints
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Sep 22 - Holiday
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Sep 25 - L06
Complex Pipelining: Superscalar and Scoreboarding
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Sep 27 - L07
Out of Order Execution and Register Renaming
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Sep 29 - Tutorial Session
Lab 1 DUE
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Oct 2 - L08
Branch Prediction
Lab 2 Out
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Oct 4 - L09
Speculative Execution and Recovery
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Oct 6 - Tutorial Session
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Oct 9 - Holiday
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Oct 11 - L10
Advanced Memory Operations
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Oct 13 - Quiz 1
Up to L09
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Oct 16 - L11
Multithreading
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Oct 18 - L12
Cache Coherence (I)
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Oct 20 - Tutorial Session
Lab 2 DUE
Lab 3 Out
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Oct 23 - L13
Cache Coherence (II)
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Oct 25 - L14
Memory Consistency Models
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Oct 27 - Tutorial Session
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Oct 30 - L15
On-chip Networking (I)
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Nov 1 - L16
On-chip Networking (II)
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Nov 3 - Tutorial Session
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Nov 6 - L17
VLIW
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Nov 8 - L18
SIMD and Vector Processors
Lab 3 DUE
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Nov 10 - Holiday
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Nov 13 - L19
GPU Architectures
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Nov 15 - L20
Reliability
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Nov 17 - Quiz 2
Up to L16
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Nov 20 - L21
Transactional Memory
Lab 4 Out
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Nov 22 - Holiday
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Nov 24 - Holiday
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Nov 27 - L22
Virtualization
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Nov 29 - L23
Security
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Dec 2 - Tutorial Session
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Dec 4 - L24
Accelerators (I)
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Dec 6 - L25
Accelerators (II)
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Dec 8 - Tutorial Session
Lab 4 DUE
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Dec 11 - L26
Future Trends
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Dec 13 - Quiz 3
(In class) Up to L25
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