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Wednesday |
Friday |
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Sep 05
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Sep 07 - L01
Introduction
Take Self-Assessment Test!
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Sep 09 - Tutorial Session
Hardwired, Single-cycle ISA Implementation
Self-Assessment Test DUE
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Sep 12 - L02
Instruction Set Architectures and Cache Organization
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Sep 14 - L03
Memory Management: From Absolute Addresses to Demand Paging
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Sep 16 - Tutorial Session
Instruction Pipelining
Lab 1 Out
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Sep 19 - L04
Modern Virtual Memory
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Sep 21 - L05
Instruction Pipelining: Hazard Resolution and Timing Constraints
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Sep 23 - Holiday
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Sep 26 - L06
Complex Pipelining: Superscalar and Scoreboarding
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Sep 28 - L07
Out of Order Execution and Register Renaming
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Sep 30 - Tutorial Session
Lab 1 DUE
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Oct 3 - L08
Branch Prediction
Lab 2 Out
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Oct 5 - L09
Speculative Execution and Recovery
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Oct 7 - Tutorial Session
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Oct 10 - Holiday
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Oct 12 - L10
Advanced Memory Operations
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Oct 14 - Quiz 1
Up to L09
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Oct 17 - L11
Multithreading
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Oct 19 - L12
Cache Coherence (I)
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Oct 21 - Tutorial Session
Lab 2 DUE
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Oct 24 - L13
Cache Coherence (II)
Lab 3 Out
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Oct 26 - L14
Memory Consistency Models
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Oct 28 - Tutorial Session
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Oct 31 - L15
On-chip Networking (I)
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Nov 2 - L16
On-chip Networking (II)
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Nov 4 - Tutorial Session
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Nov 7 - L17
VLIW
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Nov 9 - Quiz 2
Up to L16
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Nov 11 - Holiday
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Nov 14 - L18
SIMD and Vector Processors
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Nov 16 - L19
GPU Architectures
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Nov 18 - Tutorial Session
Lab 3 DUE
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Nov 21 - L20
Reliability
Lab 4 Out
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Nov 23 - L21 (Optional)
Transactional Memory (Asynchronous)
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Nov 25 - Holiday
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Nov 28 - L22
Security
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Nov 30 (Canceled)
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Dec 2 - Tutorial Session
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Dec 5 - L23
Virtualization
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Dec 7 - L24
Accelerators (I)
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Dec 9 - Tutorial Session
Lab 4 DUE
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Dec 12 - L25
Accelerators (II)
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Dec 14 - Quiz 3
(In class) Up to L24, excluding L21, L23
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