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- L-01: Introduction & History of Calculation and Computer Architecture (pdf)
- L-02: Influence of Technology and Software on Instruction Sets: Up to the dawn of IBM 360 (pdf)
- L-03: Hardwired, Single-cycle ISA Implementation (pdf)
- L-04: Instruction Pipelining and Hazards (pdf)
- L-05: Instruction Pipelining: Hazard Resolution and Timing Constraints (pdf)
- L-06: Caches (pdf)
- L-07: Memory Management from Absolute Addresses to Demand Paging (pdf)
- L-08: Modern Virtual Memory Systems (pdf)
- L-09: Complex Pipelining (pdf)
- L-10: Out-of-Order Execution, Register Renaming and Exceptions (pdf) (OoO Example: pptx)
- L-11: Branch Prediction (pdf)
- L-12: Speculative Execution (pdf) (Physical Register Management Example: pptx)
- L-13: Advanced Memory Operations (pdf)
- L-14: Multithreading Architectures (pdf)
- L-15: On-chip Networking (I) (pdf | split pdf)
- L-16: On-chip Networking (II) (pdf | split pdf)
- L-17: Cache Coherence (I) (pdf | split pdf)
- L-18: Cache Coherence (II) (pdf) (Directory Protocol Example with Animations: pptx)
- L-19: Memory Consistency Models (pdf | split pdf)
- L-20: Transactional Memory (pdf | split pdf)
- L-21: Microcoded and VLIW Processors (pdf)
- L-22: Vector Computers (pdf)
- L-23: Graphics Processing Units (GPUs) (pdf)
- L-24: Reliability (pdf)
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