% Title of ISCA paper

\date{}

\title{{\bf {\archname}: A Multithreaded Massively Parallel Architecture}}

\author{
 {\it R. S. Nikhil} $^{00}$ \\ Digital Equipment Corp.
\and
 {\it G. M. Papadopoulos} $^{01}$ \\ MIT
\and
 {\it Arvind} $^{11}$ \\ MIT
}

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\begin{abstract}

What should the architecture of each node in a general purpose,
massively parallel architecture (MPA) be?  We frame the question in
concrete terms by describing two fundamental problems that must be
solved well in any general purpose MPA.  From this, we systematically
develop the required logical organization of an MPA node, and present
some details of {\archname} (pronounced {\em Start}), a concrete
architecture designed to these requirements.  {\archname} is a direct
descendant of dynamic dataflow architectures, and unifies them with
von Neumann architectures.  We discuss a hand-compiled example and
some compilation issues.

\end{abstract}

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$^{00}$This work was done while the author was at MIT.
{\em Address\/}: Digital Cambridge Research Laboratory,
One Kendall Square, Bldg 700, Cambridge, MA 02139, USA; \\
{\em email\/}: {\tt nikhil@crl.dec.com};
{\em phone\/}: {1 (617) 621 6639} \\
\\
$^{01,11}${\em Address\/}: MIT Laboratory for Computer Science, \\
545 Technology Square, Cambridge, MA 02139, USA; \\
{\em email\/}: {\tt \{greg,arvind\}@mit.edu}; {\em phone\/}: 1 (617) 253 \{2623,6090\} \\
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\\
Funding for the work at MIT is provided in part by the Advanced
Research Projects Agency of the Department of Defense under Office of
Naval Research contract N00014-89-J-1988. \\
\\
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