\begin{thebibliography}{99}
\vspace {-0.6pc}

\bibitem {WeberGupta} Wolf-Dietrich Weber and Anoop Gupta.  Exploring the
Benefits of Multiple Hardware Contexts in a Multiprocessor
Architecture: Preliminary Results. In Proceedings of 16th Annual
International Symposium on Computer Architecture, IEEE, June 1989,
pages 273-280.

\bibitem {Anant} Anant Agarwal. Performance Tradeoffs in
Multithreaded Processors. IEEE Transactions on Parallel and
Distributed Systems, Vol. 3, No. 5, September 1992, Pages 525-539.

\bibitem {Culler} David E. Culler, Anurag Sah, Klaus Erik Shauser,
Thorsten von Eicken and Jhen Wawrzynek. Fine-grain Parallelism with
Minimal Hardware Support: A Compiler-Controlled Threaded Abstract
Machine. In Proceedings of 19th Annual International Symposium on
Computer Architecture, IEEE, June 1991, pages 164-175.

\bibitem {CM5} Charles E. Leiserson, Z. Abuhamedeh, D. Douglas, C. Feynman, 
M. Ganmukhi, J. Hill, W. Hillis, B. Kuszmaul, M. Pierre, D. Wells, M.
Wong, S. Yang and R. Zak. The Network Architecture of the Connection
Machine CM-5. In Proceedings of ACM Symposium on Parallel Algorithms
and Architectures, 1992.

\bibitem {Tera} R. Alvenson, D. Callahan, D. Cummings, B. Koblenz,
A. Porterfield and B. Smith. The Tera Computer System. In Proceedings
of International Conference on Supercomputing, June 1990.

\bibitem {JMachine} William J. Dally, L. Chao, A. Chien, S. Hassoun, 
W. Horwat, J. Kaplan, P. Song, B. Totty and S. Wills. Architecture of
a Message-Driven Processor. In Proceedings of 14th Annual
International Symposium on Computer Architecture, IEEE, June 1987,
pages 189-196.

\bibitem {Alewife} Anant Agarwal, Beng-Hong Lim, David Kranz and 
John Kubiatowicz. APRIL: A Processor Architecture for Multiprocessing.
In Proceedings of 17th Annual International Symposium on Computer
Architecture, IEEE, June 1990

\bibitem {Start} Rishiyur S. Nikhil, Gregory M. Papadopoulos and Arvind. 
*T: A Multithreaded Massively Parallel Architecture. 20th Annual
International Symposium on Computer Architecture, IEEE, June 1992, pages
156-167

\bibitem {HEP} B. J. Smith. A Pipelined, Shared Resource MIMD Computer. 
In Proceedings of 1978 International Conference on Parallel
Processing, 1978, Pages 6-8.

\bibitem {activeM} Thorsten von Eicken, David E. Culler, 
Seth Copen Goldstein, Klaus Erik Shauser. Active Messages: a Mechanism
for Integrating Communication and Computation. In proceedings of 20th
Annual International Symposium on Computer Architecture, IEEE, June
1992, pages 256-266.

\bibitem {Boothe92} Bob Boothe, Abhiram Ranade. Improved Multithreading 
Techniques for Hiding Communication Latency in Multiprocessors. In
proceedings of 20th Annual International Symposium on Computer
Architecture, IEEE, June 1992, pages 214-223.

\bibitem {Keckler92} Stephen W. Keckler, William J. Dally. Processor
 Coupling: Integrating compile Time and Runtime Scheduling for
Parallelism. In proceedings of 20th Annual International Symposium
on Computer Architecture, IEEE, June 1992, pages 202-213.

\bibitem {Monica} Monica S. Lam, Edward E. Rothberg and Michael E.
Wolf. The Cache Performance and Optimizations of Blocked Algorithms.
In Proceedings of 19th Annual International Symposium on Computer
Architecture, IEEE, June 1991, pages. 63-74.

\bibitem {Saavedra} Rafael H. Saavedra-Barrera, David E. Culler and
Thorstem von Eicken. Analysis of multithreaded architectures for
parallel computing. In proceeding of 2nd Annual ACM Symposium on
Parallel Algorithms and Architectures, IEEE, July, 1990, pages.169-177.

\bibitem {Denning} Peter J. Denning. The Working Set Model for Program
Behavior. Communications of the ACM, Vol. 11, No. 5, November 1968,
Pages 323-333.

\bibitem {Thiebaut} Dominique Thiebaut. On the Fractal Dimension of
Computer Programs and its Application to the Prediction of the Cache
Miss Ratio. IEEE Transactions on Computers, Vol. 38, No.7, July 1989,
Pages 1012-1026.

\bibitem {Kobayashi} Makoto Kobayashi, Myron MacDougall. The Stack
 Growth Function: Cache Line Reference Models. IEEE Transactions of
computers, Vol. 38, No. 6, June 1989, pages 798-805.

\bibitem {Agarwal} Anant Agarwal, Mark Horowitz and John Hennessy.
An Analytical Cache Model. ACM Transactions on Computer Systems, Vol.
7, No. 2, May 1989, Pages 184-215.

\bibitem{Stone} Harold S. Stone. High-Performance Computer
Architecture. 2nd-edition. Addison-Wesley, 1990, page 81.


\end{thebibliography}

