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\begin{document}
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%%
\covertitle{StarT the Next Generation: Integrating Global Caches and
Dataflow Architecture \\}
\title{StarT the Next Generation: Integrating Global Caches and
Dataflow Architecture \\[2 ex]}
\author{Boon Seong Ang, Arvind, and Derek Chiou\\ Laboratory for
Computer Science\\ Massachusetts Institute of Technology}
\coverauthor{Boon Seong Ang, Arvind, and Derek Chiou}

\trnumber{CSG Memo 354}
\researchcredit{This paper describes research done at the Laboratory for Computer
Science of the Massachusetts Institute of Technology. Funding for the
Laboratory is provided in part by the Advanced Research Projects
Agency of the Department of Defense under the Office of Naval Research
contract N00014-92-J-1310.}

\toappear{Proceedings of the ISCA 1992 Dataflow Workshop, Hamilton
Island, Australia (to be published), May 1992}


\maketitle


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%% Abstract
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\begin{abstract}

The implicitly parallel programming model provides an attractive
approach to deal with the complexity of parallel programming.
Implementing this model efficiently, especially on stock processors,
remains a big challenge, partly because of the fine granularity of the
parallelism exploited.  The Monsoon\cite{Greg-monsoon} project was
designed to address and investigate support for fine-grain
parallelism, and has yielded very encouraging
results\cite{monsoon-perf93}.

Our experience with Monsoon and
*T\cite{StarT92,Supercomputing93-start}, a followup project after
Monsoon, suggests that provision for global shared memory is an area
where both the Monsoon and *T architectures can be improved.  Starting
with the split-phase approach used in Monsoon and *T, we propose to
augment global memory access by including coherent global caches.  

The rapid improvements in stock microprocessors, and the high cost and
effort required to develop a competitive microprocessor, presents
practical constraints on what can be built in any experimental
architecture project.  We propose a machine that attempts to include
as many of the desired features as possible within the
constraint of using a stock microprocessor.  This machine will allow
us to continue research into the dataflow approach to parallel
computing as well as provide a prototype of a commercial product.

\end{abstract}

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%\section{Introduction}
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%\label{sec:intro}
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\input{intro}

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%\section{Parallel Programming}
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%\label{sec:parallel-programming} 
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\input{parallel}

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%\section{Fine Grain Parallel Programs on Stock Hardware}
%% ----------------------------------------------------------------------------
%\label{sec:id-on-stock}
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\input{id-on-stock}

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%\section{Monsoon: a Proof-of-concept Dataflow Machine.}
%%----------------------------------------------------------------------------
%\label{sec:monsoon}
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\input{monsoon}

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%\section{*T: Modified stock processors}
%% ----------------------------------------------------------------------------
%\label{sec:Start0-1}
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\input{start0}

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%\section{A Practical, Stock Microprocessor Based Machine}
%% ----------------------------------------------------------------------------
%\label{sec:realizable-machine}
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\input{StarT2}

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%\section{Conclusion}
%% ----------------------------------------------------------------------------
%\label{sec:conclusion}
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\input{conclusion}

\input{acks}

\input{code}
\bibliographystyle{abbrv}
\bibliography{/bk/derek/tex/short-abbrevs,arch}
%\bibliography{/bk/derek/tex/short-abbrevs,arch,/bk/derek/tex/kt}

\newpage
\tableofcontents

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\end{document}
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