%% - Recapture what *T-ng is:
%%   * a real world machine, intended as an evolutionary way to
%%     introduce parallel processing by providing machines with dual
%%     personalities.  
%%   * not the be-all-end-all machine, but will be generally available
%%     and allow people to experiment with parallel processing. 
%%   * layering parallel processing support on top of stock commercial
%%     system.  
%%   * redesigned from *T within a year.  
%%  
%% - current status:
%%   * the high level hardware design is almost frozen.
%%   * expect machine at the end of 95. 
%%   * intensive software effort to provide simulators, compilers,
%%     cache coherence protocol, performance monitoring and
%%     evaluation, and more theoretical work on consistency model
%%     taking place.  
%%   * list some language efforts.  
%% 
%%------------------------------------------------------------------------
\section{Current Status and Conclusions}
%%------------------------------------------------------------------------
\label{sec:status-conclusion}
%%------------------------------------------------------------------------

\start/'s delivery schedule is broken into 3 phases.  Phase 1 will be
delivered to MIT at the end of 1995 and consist of 8 sites, each
containing 4 NES boards.  The Phase 1 NES boards will communicate with
their NIU's at either a third or a half of the processor clock rate.
The ACD will run at a fourth of the processor clock rate, forcing the
memory bus to run at that speed when the ACD is enabled (and at L2
speeds otherwise).  The ACD and NIU will be built from off-the-shelf
parts ({\em e.g.}, FPGA's and dual-ported SRAM's).  The 620 clock rate
may have to be reduced slightly to accommodate the ACD and NIU.

Phase 2 will raise the 620 processor and bus to their maximum rated
speed and the NIU clock at one half of the 620 clock.  The ACD
clock-speed remain a factor of 4 slower than the 620 necessitating the
620 L3 bus to run at that speed when the ACD is turned on.  Phase 2 is
due in the middle of 1996.

Phase 3 will boost ACD clock rate to one half of the 620 clock rate,
making the SMP sites of the machine run at full commercial speeds even
when the ACD is turned on.  Phase 3 is currently planned for delivery
perhaps in September of 1996, but will be influenced by results from
experiments conducted on the phase 1 machine.

\start/ is a step away from networks of workstations, capturing most
of their advantages while significantly out-performing them.  \start/
will deliver very aggressive message passing performance and will
provide mechanisms to experiment with cache-coherent shared memory.
Intensive effort to develop simulators, compilers, operating system
support and coherency protocols are already underway.  \start/ should
be a cost-effective, realistic platform for research as well as
commercial parallel computing.

%%------------------------------------------------------------------------
%% END
%%------------------------------------------------------------------------
