%% This section covers 
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\section{Memory Systems in Modern Microprocessors}
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\label{sec:processor}
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The current generation of high-end RISC microprocessors -- such as the
DEC Alpha EV5, PowerPC 620 and MIPS R10000 --- delivers well over 200
Specint92 and 300 Specfp92 or more.  This level of throughput is
achieved with a combination of fast clock rates and aggressive
superscalar execution.  As a result, a complete reworking of the
memory system to meet the increased memory-bandwidth demand is
required.

\subsection{Multi-level Cache Hierarchies}

The simplest way to increase perceived memory bandwidth is to
establish a wide, high-speed datapath to the processor's primary
cache.  In order to do so, modern processors contain small (well under
100 kilobytes) level-one (L1) instruction and data caches on the
processor chip itself.  These caches have wide, low-latency datapaths
to the central processing unit and are pipelined to increase
throughput.  Set associativity of four or greater is often employed to
compensate for the limited size of these L1 caches.  However, these L1
caches are too small to get high enough hit rates to effectively mask
cache-miss latencies on systems where the system clocks are two to
four times slower than the processor clock.

As a remedy, current generations of RISC microprocessors provide a
dedicated path to a large off-chip level 2 (L2) cache {\em in addition
to} the the standard L3 path to DRAM.  A separate path is provided to
eliminate the need for an external cache-controller and to improve
performance\footnote{Of course, support for snooping must be provided
for L3 traffic.}.  All aforementioned processors provide a dedicated
L2 path that directly connects to high-speed external cache RAM's.
All the necessary cache management circuitry are build into the
processor itself.  This cache interface is clocked independently from
the bus interface and offers shorter access latency.  These external
L2 caches are usually direct-mapped and are strictly inclusive of the
on-chip L1 cache contents.

%% [This line is redundant with second sentence of above paragraph:]
%% Providing a separate L2
%% interface and the cache-controller inside of the processor eliminates the
%% need for a separate high-speed cache controller which serves as a bridge
%% between the processor and memory bus.

\subsection{Split-phased Memory Bus Cycle}

The system memory bus is doubly-taxed by current processor design due
to the addition of shared-memory support for symmetric multiprocessing
(SMP).  Not only is the already increased memory traffic from a single
processor multiplied by the degree of multiprocessing, the bus must
also accommodate cache-coherence traffic.  The traditional {\em
tenured} bus handshake in which the memory requester occupies the bus
until the memory responds does not provide sufficient bandwidth for a
multi-master bus coupled to relatively long-latency slave devices.

To reduce the bus occupancy of memory requests, modern processors
support bus protocols where address and data bus are arbitrated
separately, dividing the address-cycle, and data-cycle of a single bus
operation into independent events.  In a simple pipelinable,
split-phased bus, after a an address-cycle has completed, the next
address-cycle can start immediately, before the data-cycle of the
previous address-cycle has even started.  In this protocol, the only
guarantee is that the order of the data bus events corresponds
precisely to the order of address bus events.  To relax the protocol
further, as is done in a true split-phased bus, data events can
complete out-of-order with respect to the address events.  An
identifying tag must be assigned to each address and data event pair
to establish a correlation between a responding data-cycle and its
requesting address-cycle.  In general, a split-phase bus also needs
flow control, so that both master, slave devices and snoopers can
avoid queue overruns or other resource exhaustion.

\subsection{Weak Ordering of Reads and Writes}

In order to improve performance, modern microprocessors allow multiple
reads and writes to be in progress at the same time.  These reads and
writes may start or complete on the bus out of order with respect to
the instruction stream.  These processors must provide a mechanism to
allow the user to enforce ordering of memory operations.  When a
processor is writing to an I/O device, for example, it is essential
for some ordering to be maintained.  Some ordering mechanism is
required, such as a ``local barrier'' instruction that ensures
previous writes executed on a processor complete before new reads or
writes are allowed to execute.  When a processor is running in an SMP,
it may be important to ensure that a processor's write is seen by all
processors before that processor continues.  In that case, some
``global barrier'' mechanism is required.  These operations tend to be
very expensive since they can sequentialize instruction
execution\footnote{Sequentializing instruction execution is expensive
because the next instruction has to wait for all the functional unit
and memory-system pipelines to drain.}. The PowerPC architecture
provides only the global barrier, in the form of the \sync/
instruction.  Since a global barrier also performs local barrier
functionality, a \sync/ can be used to in place of a local barrier.

Such reordering of memory operations can be problematic if one desires
to use the fast, reordering memory path to access special devices such
as a network interface unit.  Since most standard I/O units are
accessed seldomly, it is acceptable to use synchronizing instructions
when accessing them.  However, for devices that are both low-overhead
and are accessed frequently, such as the \start/ NIU, the penalties of
using sequentializing instructions are quite noticeable.  In order to
achieve high performance, it is necessary to find ways to minimize or
eliminate synchronization overheads.  


