Lab Assignments
- Startup guide for the labs
- Lab 1 - Multiplexers and Adders (Due: Sept. 18)
- Lab 2 - Multipliers (Due: Sept. 22)
- Lab 3 - FFT (Due: Oct. 1) [FFT Presentation pptx pdf]
- Lab 4 - FIFOs (Due: Oct. 8)
- Lab 5 - SMIPS Introduction - Multi-Cycle and Two-Stage Pipeline (Due: Oct. 20)
- Lab 6 - SMIPS 6-stage Pipeline and Branch Prediction (Due:
Oct. 31Nov. 3) - Lab 7 - SMIPS with DRAM and Caches (Due:
Nov. 10Nov. 12Nov. 14) - Lab 8 - SMIPS with Exceptions (Due: Nov. 21)
Final Project
The final project for this semester is to build a non-blocking cache hierarchy for an out-of-order processor. This project has been split into three parts:
- Part 0: Understanding non-blocking caches and cache coherency [pdf] [pptx]
- This is an ungraded exercise to practice your understanding of the material for the project.
- Complete these tables of executions before the lecture on Friday, November 21st.
- Solutions: [pdf] [pptx]
- Part 1: Constructing a non-blocking cache hierarchy
[pdf]
- This part of the project will be done using a test bench to simulate cache requests the processor.
- Initial code can be found in your group git repo or here: [tar.gz] [patch1 tar.gz]
- Due: Tuesday, December 2nd
- Part 2: Integrating the non-blocking cache hierarchy into an out-of-order processor
[pdf]
- Due: Wednesday, December 10th