6.884 Complex Digital Systems

Term: Spring 2005
Instructors: Professor Arvind and Professor Krste Asanovic
Prerequisites: 6.001 and 6.004 or equivalent
Credit: 5-5-2 H-Level
Lectures: MWF 1-2:30, 24-307

A project-oriented course to teach new methodologies for designing multi-million-gate CMOS VLSI chips using high-level synthesis tools in conjunction with standard commercial EDA tools. The emphasis is on modular and robust designs, reusable modules, correctness by construction, architectural exploration, and meeting the area, timing, and power constraints within standard cell and FPGA frameworks.

The first half of the course includes lectures on technology and scaling; area, delay, and power dissipation of gates and interconnect; VLSI implementation styles emphasizing cell-based ASICs and FPGAs; hardware description languages including Verilog and Bluespec; clocking, power distribution, packaging, I/O, and fabrication testing. In addition, weekly labs using commercial EDA tools will prepare students for the class project.

In the second half of the course, students will work in small groups on large chip design projects with regular advisory meetings with the instructors.