Most of the documents referenced by this page are available in PDF format. On Athena, Mozilla is already configured with the necessary plug-in to view PDF files. To configure the browser on your machine you may need to download and install the Adobe Acrobat Reader.
Lectures and Tutorials
These slides are made available for the convenience of our students. Others may use them for noncommercial purposes as long as MIT and the original authors are appropriately credited.
- L01: Overview [PDF, PDF-4UP]
- L02: Digital Design Using Verilog [PDF, PDF-4UP]
- L03: CMOS Technology and Logic Gates [PDF, PDF-4UP]
- T01: Verilog Simulation Tutorial I [PDF, PDF-4UP]
- L04: Wires [PDF, PDF-4UP]
- L05: Synthesis [PDF, PDF-4UP]
- T02: Verilog Simulation Tutorial II [PDF, PDF-4UP]
- L06: Clocking [PDF, PDF-4UP]
- L07: Bluespec-1: Motivation [PDF-2UP]
- L08: Bluespec-2: Designing with Rules [PDF-2UP]
- L09: Bluespec-3: Modules & Interfaces [PDF-2UP]
- L10: Bluespec-4: Rule Scheduling and Synthesis [PDF-2UP]
- T03: Bluespec Tutorial [PDF-2UP]
- L11: Power [PDF, PDF-4UP]
- L12: Bluespec-5: Processors [PDF-2UP]
- L13: Bluespec-6: Modularity and Performance [PDF-2UP]
- L14: Transaction-Level Design [PDF, PDF-4UP]
- L15: Testing [PDF, PDF-4UP]
There will be one 90 minute quiz on Friday, March 18 in class. The quiz is closed book.
See the schedule for due dates and the course information for class policies on turning in labs and collaboration. The SMIPS Processor Specification contains details on the SMIPS ISA which is used in several of the labs.
- Lab 1: RTL Model of a Two-Stage MIPS Processor [PDF]
- Lab 2: ASIC Implementation of a Two-Stage MIPS Processor [PDF, Results]
- Lab 3: Bluespec Model of a Network Linecard [PDF]
For the verilog examples, the source and scripts necessary for building and testing them can all be found in the course locker.