MIT's riscy expedition

Our expedition into the RISC-V world goes in several directions that are listed here.

Architectural

Previous Work:

• MIT 6.175 - Constructive Computer Architecture
• Out-of-order multicore SMIPS processor
• In-order pipelined RISC-V processor booting linux with MMU, with an FPGA implementation.

Expedition :

• Integrating previous work into RISC-V processor
• Additional architectural explorations

Accelerators

Previous Work:

• BlueDBM - 20 node cluster - FPGA w/ large flash memory store per node

Expedition:

• Integrating RISC-V cores with convolutional neural network accelerators into the BlueDBM machine

Memory Consistency Models

Previous Work:

• WMM - Weak Memory Model with intuitive execution semantics

Expedition:

• Evaluate WMM with RISC-V processor

Formal Verification/Specification

Previous Work:

• Formally verified cache coherency protocol
• Tandem verified processor

Expedition:

• Integrate formally verified parts into the RISC-V processor
• Formally specify enough of the ISA for verification
• Prove correctness of architectural improvements such as out-of-order execution

ASIC Implementations

Previous Work:

• Made processors for FPGA and ignored ASIC performance

Expedition:

• Tune portions of the architecture for efficient ASIC implementation