6.375 Schedule

Spring 2006

  Feb 08
L01 Introduction
[Arvind] 		Feb 10
L02 Verilog 1 - Fundamentals
[Chris]
Feb 13
L03 Verilog 2 - Design Examples
[Chris] 		Feb 15
L04 CMOS Transistors, Gates, and Wires
[Chris] 		Feb 17
L05 Standard-Cell ASICs: Synthesis, Placement, and Routing
[Srini]
Feb 21
(Tuesday)
L06 Handling Physical Design Issues in ASIC Toolflows
[Chris] 		Feb 22
No Lecture
Extra TA office hours in 38-301 		Feb 24
L07 Bluespec 1 - Motivation
[Arvind]
Lab 1 due
Feb 27
L08 Bluespec 2 - Types
[Arvind] 		Mar 01
L09 Bluespec 3 - 802.11a Example
[Arvind] 		Mar 03
Potpourri Lecture/Tutorial
[Chris+Michael]
Mar 06
L10 Bluespec 4 - Rule Scheduling + Synthesis
[Arvind] Lab 2 due 		Mar 08
L11 Bluespec 5 - Rule Scheduling
[Arvind] 		Mar 10
L12 Bluespec 6 - Processors
[Arvind]
Mar 13
L13 Bluespec 7 - Language Semantics
[Arvind]
Mar 15
L14 Bluespec 8 - Modules and Interfaces
[Arvind] 		Mar 17
Potpourri Lecture/Tutorial
[Chris]
Mar 20
Guest Lecture: Multiple Clock Domains in BSV
[Joe Stoy]
Lab 3 due 		Mar 22
General Discussion on Rule Scheduling [Arvind]		 Mar 24
** Quiz **
Preliminary Project Proposals Due
Mar 27
Spring Break 		Mar 29
Spring Break 		Mar 31
Spring Break
Apr 03 Apr 05
Team meetings on preliminary proposals (All Groups)		 Apr 07
(1) Project Proposals Due
Apr 10
Team meetings on high-level design + test strategy (Groups 1,2,3) 		Apr 12
Team meetings on high-level design + test strategy (Groups 4,5,6) 		Apr 14
(2) High-Level Design + Test Strategy Doc Due
Apr 17,18
Patriots Day 		Apr 19
Guest Lecture 		Apr 21
Apr 24
Team meetings on microarchitecture (Groups 1,2,3) 		Apr 26
Team meetings on microarchitecture (Groups 4,5,6) 		Apr 28
(3) Initial bluespec design working, Microarchitecture Doc Due
May 01
Team meetings on design exploration (Groups 1,2,3) 		May 03
Team meetings on design exploration (Groups 4,5,6) 		May 05
(4) Design Exploration Doc Due
Multiple alt designs working in CVS
May 08 May 10 May 12
May 15 May 17
Project Presentations (All Groups) 		May 18
(Thursday)
Final Report Due