| Prerequisites | Students should feel comfortable programming in some object oriented language (e.g., Java, C++) or functional language (Haskell, ML, Scheme). A rudimentary knowledge of basic logic design (6.004) and undergraduate-level knowledge of Computer Architecture (Hennessy & Patterson books) is assumed. As with all project courses the end of term crunch can be a problem, so it would be unwise to take this course with another which also has a significant design project due at the end of the term. |
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| Lectures and Tutorials | Lectures will be from 2:30 PM to 4:00 PM every Monday, Wednesday, and Friday in Room 34-301. Friday class sessions are designated as tutorials. In the second half of the term each project team will be expected to meet once per week with the instructors. These meetings will be scheduled during the normal lecture times. |
| Grades | Grades will be based on labs (30%), project milestones (25%), a final project demonstration (20%), and the final completed project (25%). |
| Lab Assignments | Labs are to be done individually and are designed to help you learn the skills you'll need to complete the final project. Some of the labs are too long to be done the night before the due date, so plan accordingly. Late labs will not be accepted. See the schedule for details on when labs are due. Feel free to get help from others, but the work you hand in should be your own. |
| Final Project | Projects will be done in groups of 2 to 3 students. Each group will be assigned a senior graduate student as a mentor. The mentor will provide oversight and advice to the project group. Several milestone reports (two to three pages) will be due periodically. These milestone reports are (1) Project Proposal, (2) High-level Design and Test Strategy, (3) Detailed Micro-Architectural Design, (4) Design Space Exploration. Final project presentations will take place during the last week of classes. The final report (15 to 20 pages) is due May 15. There are no extensions. |
| EDP/TQE | This course is worth 12 Engineering Design Points (EDPs). See Course VI Undergraduate Programs: Policies, Procedures, and Organization for more information on EDPs. Course 6.375 may satisfy one of your Technical Qualifying Examination (TQE) requirements for the Systems Group. See Graduate Office Memo 3805 for more info on the TQE. |
| Lab Resources | Dedicated Athena servers, some with FPGAs attached, can be used for the labs. All tools can be run out of the course locker on any Athena/Linux machine. See Lab Resources for more information on the computing resources available for the class. |
| Collaboration and Academic Honesty Policy |
Collaboration amongst students to understand the course material is strongly encouraged, however any work you turn in must be your own. |
| Course Reading Material | There is no text book for the course. Books and links which would provide useful reference are listed on the resources page. |
| Computer Communication | The TAs and instructors can be reached for questions, comments, etc. via email at 6.375-admin mit edu. Questions which are specific to the Bluespec language or compiler can also be directed to bluespec-support mit edu. We will mail all announcements, labs, clarifications to assignments, answers to common questions, etc. to the course email list at 6.375-students mit edu. |
Digital Systems
