Lectures
- L01: Combinational Circuits [ L01-CombinationalCkts.pptx ] [ L01-CombinationalCkts.pdf ]
- L02: Complex Combinational Circuits [ L02-ComplexCombinationalCkts.pptx ] [ L02-ComplexCombinationalCkts.pdf ]
- L03: Sequential Circuits [ L03-SequentialCircuits.pptx ] [ L03-SequentialCircuitsRev.pdf ]
- L04: Complex Sequential Circuits - IFFT [ L04-IFFT.pptx ] [ L04-IFFT.pdf ]
- L05: Folding and Pipelining Complex Circuits [ L05-PipeliningCombCkts.pptx ] [ L05-PipeliningCombCkts.pdf ]
- L06: SMIPS ISA [ L06-SMIPS.pptx ] [ L06-SMIPS.pdf ]
- L07: Single-cycle implementation [ L07-SingleCycleImplementation.pptx ] [ L07-SingleCycleImplementation.pdf ]
- L08: Multi-cycle implementation [ L08-MultiCycleImplementations.pptx ] [ L08-MultiCycleImplementations.pdf ]
- L09: Simple Pipelined Architectures [ L09-SimplePipelinedArchitectures.pptx ] [ L09-SimplePipelinedArchitectures.pdf ]
- L10: Data Dependencies in Pipelined Architectures [ L10-DataDependencies.pptx ] [ L10-DataDependencies.pdf ]
- L11: Six stage pipeline implementation [ L11-SixStage.pptx ] [ L11-SixStagePrint.pdf ]
- L12: Bypass implementation [ L12-Bypassing.pptx ] [ L12-BypassingPrint.pdf ]
- L13: Caches Part1 [ L13-Caches_NewInterface.pptx ] [ L13-Caches_NewInterface.pdf ]
- L14: Caches Part2 [ L14-CachesPart2.pptx ] [ L14-CachesPart2.pdf ]
- L15: Caches Part3 [ L15-CachesPart3.pptx ] [ L15-CachesPart3.pdf ]
- L16: Branch Prediction Part1 [ L16-BranchPrediction-1.pptx ]
- L17: Branch Prediction Part2 [ L17-BranchPrediction-2.pptx ]
- L18: Branch Prediction Part3 [ L18-BranchPrediction.pptx ]
- L19: Direction Prediction [ L19-DirectionPrediction.pptx ]
- L20: Predictor Integration [ L20-PredictorIntegration.pptx ]
- L21: Exceptions [ L21-Exceptions.pptx ]
- L22: Virtual Memory [ L22-VirtualMemory-Part1.pptx ]
- L23: EHR based methodology [ L23-EHRmethodology.pptx ] [ L23-EHRmethodology.pdf ]
- L24: EHR based processor pipeline and caches [ L24-Caches and Processor Pipeline.pptx ] [ L24-Caches and Processor Pipeline.pdf ]
- L25: Non-blocking caches [ L25-Non-Blocking caches.pptx ] [ L25-Non-Blocking caches.pdf ]
Lab Assignments
All lab assignments are posted on the course Wiki
- Lab 1: Barrel Shifter implementation
- Lab 2: Pipelined Barrel Shifter and Booth Multiplier implementation
- Lab 3: Linear pipeline and Circular multi-cycle FFT implementations
- Lab 4: Two stage Processor implementation
- Lab 5: Three stage Pipelined Processor implementation
- Lab 6: Six stage Pipelined Processor with bypassing
- Lab 7: Integrating a Multi-cycle ALU and Caches into a Six-stage pipeline
- Lab 8: Implementing Caches
- Lab 9: Branch Prediction
- Lab 10: TLB Implementations
Tutorials
- AWB Tutorial [ ArchitectsWorkbench.pptx ]
Other
- Beta ISA [ BetaInst.pdf ]
- SMIPS ISA Summary [ smipsSummary.pdf ]
- Detailed SMIPS ISA Specification [ smipsSpecification.pdf ]
- .emacs : Place in ~ [ .emacs ]
- Emacs mode files : Extract and Place in ~ [ emacs.tar.gz ]
- 5 stage processor code as discussed in L23 [ proc_5stg.tar.gz ]