Fall 2013
Instructors:
Arvind
Prerequisites:
6.004 or equivalent
6.005 or equivalent
Familiarity with an object-oriented language such as C++, Java or a typed functional language such as ML, Haskell
Credit:
3-8-1. Eight Engineering Design Points
Lectures: MWF 3:00, 4-153
6.S195 is a new subject to learn the fundamental principles of computer architecture via implementation of different versions of pipelined machines with caches, branch predictors and virtual memory. Emphasis on writing and evaluating architectural descriptions that can be both simulated and synthesized into real hardware or run on FPGAs. The use and design of test benches. Weekly labs. Intended for students who want to apply computer science techniques to complex hardware design.
Topics include combinational circuits including adders and multipliers, multi-cycle and pipelined functional units, RISC Instruction Set Architectures (ISA), non-pipelined and multi-cycle processor architectures, 2-to-10 stage in-order pipelined architectures, processors with caches and hierarchical memory systems, TLBs and page faults, I/O interrupts.