Computer-Aided Automation Group

Projects

		Aries Architecture Exploration - The AAE project works the hardware side of distributing intelligence and control to home and office devices. It's goal is to define an architecture and to implement an automatic retargetable code generation and simulation for embedded systems. This software-based approach to hardware design and testing will reduce the cost and time to market, while increasing the performance and functional ability of distributed dedicated processors for device intelligence and control.
		Modular Appliance Super Computer - MASC envisions a network of intelligent, controllable, and upgradable hardware devices for the home and office environments. This work centers on novel hardware and software architectures for next generation information appliances and user interfaces. On the hardware side, current efforts are based on adding both intelligence and control, embedded in low-cost replaceable modules, to home and office devices, leveraging advances from the work done on AAE, SPAM, and AVP. On the software side, MASC is defining an architecture and prototyping real-world implementations of control algorithms that incorporate device- and environment-specific information and also include human factors considerations.
		Automated Verification Project - AVP researches systems for automatically verifying the correctness of hardware description language (HDL) designs. This can best be viewed as an intelligent debugger for the types of hardware devices that will result from the Aries and SPAM projects.
		Malleable Caches - We propose to make modern microprocessor caches more malleable so as to better meet the needs of modern applications. A malleable cache permits the cache resources to be allocated in an application-specific, dynamic and adaptive fashion. Mechanisms for malleable caches can be integrated into microprocessors without sacrificing software backward compatibility. Malleable caches will provide significant improvement in the performance of data-intensive applications, and will also enable new applications on general-purpose microprocessors.
		SPAM - SPAM is a collaboration between the CAD research groups at Synopsis Corporation, Princeton University, Achen University, and MIT. This effort is developing a retargetable optimizing compiler for embedded processors. Optimization provides better performance while retargetability allows the generated code to be run on many different types of dedicated processors. This work is closely related to the AAE project.