Lab Assignments
- Startup guide for the labs
- Lab 1 - Multiplexers and Adders (Due: Sept. 18)
- Lab 2 - Multipliers (Due: Sept. 28)
- Lab 3 - FFT (Due: Oct. 7) [FFT Presentation pptx pdf]
- Lab 4 - FIFOs (Due: Oct. 14)
- Lab 5 - RISC-V Introduction - Multi-Cycle and Two-Stage Pipeline (Due: Oct. 26)
- Lab 6 - RISC-V 6-stage Pipeline and Branch Prediction (Due: Nov. 9) [Global epoch slides pptx pdf]
- Lab 7 - RISC-V with DRAM and Caches (Due: Nov. 20)
- Lab 8 - RSIC-V with Exceptions (Due: Nov. 27)
Final Project
The final project for this semester is about store queue and cache coherence. This project has been split into two parts:
Project (both part 1 and part 2) is due at 3:00pm, Wednesday, December 9th.
Final presentation (10min) at 3:00pm, Wednesday, December 9th.