6.375 Complex Digital Systems

Fall 2019

Term: Fall 2019
Instructors: Arvind
Prerequisites: 6.004 or equivalent
Credit: 5-5-2
Lectures: MWF 1-2:30, 5-234
Piazza: Link

6.375 is a project-oriented subject to teach a new method to design multi-million-gate chips using Bluespec Systemverilog (BSV) in conjunction with open-source and commercial EDA tools. The emphasis is on modular and robust designs; reusable modules; correctness by construction; architectural exploration; meeting area and timing constraints; and developing functional FPGA prototypes. This subject relies on high-level architectural knowledge and programming expertise rather than knowledge of low-level circuit design.

The first half of the subject introduces BSV, a hardware description language based on guarded atomic actions, using examples of increasing complexity. In the labs each student will learn to design accelerators for signal processing and simple pilpelined processors, first only in simulation and then on an FPGA platform. Emphasis will also be placed on development of proper infrastructure for testing designs. These labs will prepare the student for the class project that follows.

In the second half of the subject, students will work in small groups on large hardware design projects supervised by the subject staff and graduate student mentors. Past projects have included out-of-order processors, cache-coherent memory systems, advanced DRAM access schedulers, spam filters to support 1Gbps line rate, and physical layer processing of 802.11a protocol. Students will be required to develop working FPGA prototypes of their implementations.