6.884 Course Schedule

  Feb 02
L01 Introduction
[Krste] 		Feb 04
L02 Digital Design Using Verilog
[Chris]
Lab 1 assigned
Feb 07
L03 CMOS Technology + Logic Gates
[Krste] 		Feb 09
Verilog Simulation Tutoral I
[Chris] 		Feb 11
L04 Wires
[Krste]
Feb 14
L05 Synthesis
[Arvind] 		Feb 16
Verilog Simulation Tutoral II
[Chris] 		Feb 18
L06 Clocking
[Krste]
Lab 1 due
Feb 22
(Tuesday)
L07 Bluespec I
[Arvind]
Lab 2 assigned		 Feb 23
No Lecture! 		Feb 25
L08 Bluespec II
[Arvind]
Feb 28
L09 Bluespec III
[Arvind] Lab 2 due 		Mar 02
L10 Bluespec IV
[Arvind] 		Mar 04
Bluespec Tutorial
[Michael]
Lab 3 assigned
Mar 07
L11 Power
[Krste]
Hand out project choices 		Mar 09
L12 Bluespec V
[Arvind] 		Mar 11
L13 Bluespec VI
[Arvind]
Lab 3 due
Mar 14
L14 Transaction Level Design + Verification
[Krste]
Mar 16
L15 Testing
[Krste] 		Mar 18
Quiz

(0) Preliminary Project Proposals Due
Mar 21
Spring Break 		Mar 23
Spring Break 		Mar 25
Spring Break
Mar 28
Team discussion on preliminary proposals
(Groups 2,3,4)		 Mar 30
Team discussion on preliminary proposals
(Groups 1,5,6)		 Apr 01
(1) Project Proposals Due
Apr 04
Team discussion on UTL design
(Groups 2,3,6)		 Apr 06
Team discussion on UTL design
(Groups 1,4,5)		 Apr 08
(2) High-level UTL Architectural Doc Due
Apr 11
Team discussion on test strategy
(Groups 2,3,6)		 Apr 13
Team discussion on test strategy
(Groups 1,4,5)		 Apr 15
(3) Test Strategy Doc Due
Ref impl working with test harness and in CVS
Apr 18,19
Patriots Day 		Apr 20
Team discussion on RTL
(All Groups)		 Apr 22
(4) Microarchitectural Design Doc Due
Initial RTL design working and in CVS
Apr 25
Team discussion on design exploration
(Groups 2,3,6)		 Apr 27
Team discussion on design exploration
(Groups 1,4,5)		 Apr 29
(5) Design Exploration Doc Due
Multiple alternative designs working and in CVS
May 02
Final team discussion
(Groups 2,3,6)		 May 04
Final team discussion
(Groups 1,4,5)		 May 06
Project Presentations
(Groups 2,3,6)
May 09
Project Presentations
(Groups 1,4,5) 		May 11
Final Report Due