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Lectures
- L01: Complex Digital Systems [ PDF ] (02/07/07)
- L02: Verilog 1 - Fundamentals [ PDF ] (02/09/07)
- L03: Verilog 2 - Design Examples [ PDF ] (02/12/07)
- L04: Bluespec-1: Design methods to facilitate rapid growth of SoCs [ PDF ] [ PPT ] (02/14/07)
- L05: Architectural Exploration: Area-Power tradeoff in 802.11a transmitter design [ PDF ] [ PPT ] (02/16/07)
- L06: Bluespec-3: A non-pipelined processor [ PDF ] [ PPT ] (02/20/07)
- L07: Bluespec-4: Architectural exploration using IP lookup [ PDF ] [ PPT ] (02/21/07)
- L08: Blusepc-5: Dead cycles, bubbles and Forwarding in Pipelines [ PDF ] [ PPT ] (02/23/07)
- L09: Bluespec-6: Modules and Interfaces [ PPT ] (02/26/07)
- L10: Bluespec-7: Scheduling & Rule Composition [ PDF ] [ PPT ] (02/28/07)
- L11: Physical Effects: Delay [ PPT ] (03/05/07)
- L12: Clock and Power [ PPT ] (03/07/07)
- L13: VLSI CAD Flow: Logic Synthesis [ PPT ] (03/09/07)
- L14: Physical Design [ PPT ] (03/12/07)
Quiz
Lab Assignments
- Lab 1: Verilog RTL for 2-Stage SMIPSv2 Processor [ PDF ]
- Lab 2: Bluespec Implementation of a 3-Stage SMIPSv2 Processor [ PDF ]
- Lab 3 (Part I): ASIC Implementation of a 3-Stage SMIPSv2 Processor [ PDF ]
Tutorials
The following tutorials show how to use the 6.375 toolflow on Athena/Linux. See 6.375 Athena Computing Resources for more information on the computing resources available for the class.
- T01: Simulating Verilog RTL Using Synopsys VCS [ PDF ]
- T02: Using CVS to Manage Source RTL [ PDF ]
- T03: Assembly Programming for the SMIPS Processor
- T04: RTL-to-Gates Synthesis using Synopsys Design Compiler [ PDF ]
- T05: Automatic Placement and Routing using Cadence Encounter [ PDF ]
- T06: Power Analysis using Synopsys VCS and Cadence Encounter
- T07: Generating On-Chip SRAMs using RapidCompile
- T08: GAA-to-RTL Synthesis using the Bluespec Compiler [ PDF ]