Prerequisites: 6.001 and 6.004 or equivalent
Credit: 5-5-2 H-Level
Lectures: MWF 2:30-4, 32-124
Group Meetings: 32-G866
A project-oriented course to teach new methodologies for designing multi-million-gate CMOS VLSI chips using high-level synthesis tools in conjunction with standard commercial EDA tools. The emphasis is on modular and robust designs; reusable modules; correctness by construction; architectural exploration; and meeting the area, timing, and power constraints within standard-cell frameworks.
The first half of the course includes lectures on technology and scaling; area, delay, and power dissipation of gates and interconnect; standard-cell ASIC design methodologies; physical design issues such as clocking, power distribution, wire delay, and testing; and hardware description languages including Verilog and Bluespec. Occasional guest lecturers will describe their experiences building large industrial and academic chips. In addition, four lab assignments using commercial EDA tools will prepare students for the class project.
In the second half of the course, students will work in small groups on large chip design projects with regular advisory meetings with the instructors. Past projects have included out-of-order processors, cache-coherent memory systems, and advanced memory access schedulers.