| Feb 06 Introduction Handout Lab 1 |
Feb 08 Verilog 1 |
|
| Feb 11 Verilog 2 |
Feb 13 Bluespec 1 - Introduction |
Feb 15 Bluespec 2 - GCD example Lab 1 due Handout Lab 2 |
|
Feb 19 (Tuesday) No Class |
Feb 20 Bluespec 3 - Combinational Circuits & Synch. Pipelines |
Feb 22 Bluespec 4 - Architectural exploration using IP Lookup |
| Feb 25 Bluespec 5 - Modelling Processors |
Feb 27 Bluespec 6 - Modular Refinement |
Feb 29 Bluespec Review |
| Mar 03 Bluespec 7 - Scheduling and Rule Composition Lab 2 due Handout Lab 3 |
Mar 05 Bluespec 8 - Performance Issues |
Mar 07 Multiple Clock Domains |
| Mar 10 Transaction Level Design in Bluespec |
Mar 12 Discussion of Final Projects |
Mar 14 Physical Design 1 |
| Mar 17 Physical Design 2Lab 3 due |
Mar 19 Review Session |
Mar 21 ** Quiz ** Preliminary Project Proposals Due |
| Mar 24 Spring Break |
Mar 26 Spring Break |
Mar 28 Spring Break |
| Mar 31 |
Apr 02 Team meetings on preliminary proposals |
Apr 04 (1) Project Proposals Due |
| Apr 07 |
Apr 09 Team meetings on high-level design + test strategy |
Apr 11 (2) High-Level Design + Test Strategy Doc Due |
|
Apr 14, 15 Patriots Day |
Apr 16 Team meetings on microarchitecture |
Apr 18 |
| Apr 21 |
Apr 23 Team meetings on microarchitecture |
Apr 25 (3) Initial bluespec design working, Microarchitecture Doc Due |
| Apr 28 |
Apr 30 Team meetings on design exploration |
May 02 (4) Design Exploration Doc Due Multiple alt designs working in CVS |
| May 05 | May 07 Team meetings on design exploration |
May 09 |
| May 12 Preliminary project report due |
May 14 Project Presentations (All Groups) |
May 15 (Thursday) Final Report Due |
Digital Systems
