6.175 teaches the fundamental principles of computer architecture via implementation of different versions of pipelined machines with caches, branch predictors and virtual memory. Emphasis on writing and evaluating architectural descriptions that can be both simulated and synthesized into real hardware or run on FPGAs. The use and design of test benches. Weekly labs. Intended for students who want to apply computer science techniques to complex hardware design.
Topics include combinational circuits including adders and multipliers, multi-cycle and pipelined functional units, RISC Instruction Set Architectures (ISA), non-pipelined and multi-cycle processor architectures, 2- to 10-stage in-order pipelined architectures, processors with caches and hierarchical memory systems, TLBs and page faults, I/O interrupts.
MWF 3:00 pm, 34-302.
Please check back frequently as this schedule may change.
This calendar is also available on Google Calendar.
|1||Wed, Sept 6||Lecture 1: Introduction.
Lab 0 out
|Fri, Sept 8||Lecture 2: Combinational Circuits
Lab 1 out
|2||Mon, Sept 11||Lecture 3: Combinational ALU||[pptx] [pdf]|
|Wed, Sept 13||Lecture 4: Sequential Circuits||[pptx] [pdf]|
|Fri, Sept 15||Lecture 5: Modules with Guarded Interfaces||[pptx] [pdf]|
|3||Mon, Sept 18||Lecture 6: Multirule Systems.
Lab 1 due Lab 2 out
|Wed, Sept 20||Lecture 7: Conflict Matrix|
|Fri, Sept 22||Tutorial 1|
|4||Mon, Sept 25||Lecture 8:
Lab 2 due