|
|
- L-01: Introduction & History of Calculation and Computer Architecture (pdf)
- L-02: Instruction Set Architecture & Hardwired, Non-Pipelined ISA Implementation (pdf)
- L-03: Cache Organization (pdf)
- L-04: Memory Management (pdf)
- L-05: Modern Virtual Memory Systems (pdf)
- L-06: Instruction Pipelining and Hazards (pdf) (pdf animated)
- L-07: Instruction Pipelining: Hazard Resolution, Timing Constraints (pdf)
- L-08: Complex Pipelining (pdf)
- L-09: Complex Pipelining: OoO Execution, Register Renaming, Exceptions (pdf) (pdf animated)
- L-10: Branch Prediction (pdf)
- L-11: Speculative Execution (pdf) (pdf animated)
- L-12: Advanced Memory Operations (pdf)
- L-13: Multithreading Architectures (pdf)
- L-14: Cache Coherence (pdf) (pdf animated)
- L-15: Directory-Based Cache Coherence (pdf) (pdf animated)
- L-16: Memory Consistency Models (pdf)
- L-17: On-chip Networks I: Topology and Flow Control (pdf)
- L-18: On-chip networks II: Router Microarchitecture and Routing (pdf)
- L-19: Reliable Architectures (pdf) (pdf animated)
- L-20: Microcoded and VLIW Processors (pdf)
- L-21: Vector Computers (pdf)
- L-22: GPUs (pdf)
- L-23: Transactional Memory (pdf)
- L-24: Virtual Machines and Binary Translation (pdf)
|