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Lectures
- L01: Complex Digital Systems [ PDF ] [ PPT ] (02/04/09)
- L02: Verilog 1 - Fundamentals [ PDF ] [ PPT ] (02/06/09)
- L03: Verilog 2 - Design Examples [ PDF ] [ PPT ] (02/09/09)
- L04: Bluespec-1: A new design methodology [ PDF ] [ PPT ] (02/11/09)
- L05: Bluespec-2: Combinational Circuits & Simple Synchronous Pipelines [ PDF ] [ PPT ] (02/13/09)
- L06: Bluespec-3: Architectural exploration using IP lookup [ PDF ] [ PPT ] (02/16/09)
- L07: Bluespec-4: Modeling Processors [ PDF ] [ PPT ] (02/18/09)
- L08: Bluespec-5: Asynchronous Pipelines: Concurrency Issues [ PDF ] [ PPT ] (02/20/09)
- L09: Bluespec-6: Modular Refinement 1 [ PDF ] [ PPT ] (02/23/09)
- L10: Bluespec-7: Modular Refinement 2 [ PDF ] [ PPT ] (02/25/09)
- L11: FPGAs [ PDF ] [ PPT ] (02/27/09)
- L12: Project Ideas [ PDF ] [ PPT ] (03/07/09)
- L13: Bluespec-8: Multiple Clock Domains [ PDF ] [ PPT ] (03/10/09)
Lab Assignments
- Lab 1: Verilog RTL for 2-Stage SMIPSv2 Processor [ PDF ]
- Lab 2: Bluespec Implementation of a 3-Stage SMIPSv2 Processor [ PDF ]
- Lab 3: FPGA Implementation of a 3-Stage SMIPSv2 Processor [ PDF ]
Tutorials
The following tutorials show how to use the 6.375 toolflow on Athena/Linux. See 6.375 Athena Computing Resources for more information on the computing resources available for the class.
- T01: Simulating Verilog RTL Using Synopsys VCS [ PDF ]
- T02: Using CVS to Manage Source RTL [ PDF ]
- T08: GAA-to-RTL Synthesis using the Bluespec Compiler [ PDF ]
- T09: RTL-to-Gate Synthesis using the SynplifyPro [ PDF ] [ SRC ]
- T10: Synthesis and Place and Route using Quartus II [ PDF ]
- T11: System Building with SOPC Builder [ PDF ]
- T12: Embedded Programming with the NIOS II IDE [ PDF ]
- T13: Importing IP into SOPC Builder [ PDF ]