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Bluespec Workshop    
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Program Information
(The technical program will be held in 32-155)


Technical Agenda

8:30 - 9:00 - Morning Refreshments

9:00 - 9:15: Bluespec at MIT (Arvind) 15 min

9:15 - 10:30: Bluespec Product Status/Direction, 1 hour 15 min

  • Overview
  • - George Harper, Bluespec, 20 min
  • Debug Workstation - Ed Czeck, Bluespec, 20 min
  • SoC Platform
  • - Elliot Mednick, Bluespec, 20 min
  • Runtime Debugging
  • - Don Baltus, Bluespec, 20 min

    10:30-11:00: Break

    11-12:30: Performance Modeling on FPGAs
  • Performance Modeling via A-Ports,
  • Michael Pellauer and Joel Emer, Intel/MIT, 20 min
  • The Design and Implementation of FAST Module Connectors,
  • Bill Reinhart, U of Texas, 20 min
  • Architectural Emulation on FPGA Made Easy with Bluespec,
  • Eric Chung, CMU, 20 min
  • Splitting Functional and Timing Models: The Role of Bluespec,
  • Derek Chiou, U of Texas, 20 min

    12:30-1:30: Lunch

    1:30-3:00: Facilitators
  • Modular Bluespec Design Using ASIM/AWB,
  • Joel Emer and Michael Pellauer, Intel/MIT, 20 min
  • Facilitating Cross-FPGA Platform Designs Using "Virtual" Platforms,
  • Angshuman Parashar, Intel, 20 min
  • Bluespec and Co-Simulation,
  • Myron King, Nokia/MIT, 20 minutes
  • Latency Insensitive Design in a Latency Sensitive World,
  • Elliott Fleming, Nokia/MIT, 20 min

    3:00-3:30: Break

    3:30-4:30:Potpourri
  • The Power PC Models in Bluespec,
  • Pratap Pattnaik, IBM, 10 minutes
  • Bluespec at Qualcomm,
  • Suhas Pai, Qualcomm, 10 minutes
     
  • Lowering Power Consumption with Bluespec,
  • Sandeep Shukla and Gaurav Singh, Virginia Polytechnic, 20 min
  • Sudoku: Revolution Number 9... or 16... or ...,
  • Rishiyur Nikhil and Jeff Newbern, Bluespec, 20 min

    4:30-5:30
    Discussion: Feedback, Flames, Requests, ...

    Banquet at Royal East (792 Main Street, Cambridge, MA)

  • 6:00pm  Cocktails
  • 7:00pm  Dinner




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