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- L-01: Introduction & History of Calculation and Computer Architecture (pdf | split pdf)
- L-02: Influence of Technology and Software on Instruction Sets: Up to the dawn of IBM 360 (pdf | split pdf)
- L-03: Hardwired, Single-cycle ISA Implementation (pdf | split pdf)
- L-04: Instruction Pipelining and Hazards (pdf | split pdf)
- L-05: Instruction Pipelining: Hazard Resolution and Timing Constraints (pdf | split pdf)
- L-04: Instruction Pipelining and Hazards (pdf)
- L-05: Instruction Pipelining: Hazard Resolution and Timing Constraints (pdf)
- L-06: Microprogramming (pdf)
- L-07: Caches (pdf)
- L-08: Memory Management from Absolute Addresses to Demand Paging (pdf)
- L-09: Modern Virtual Memory Systems (pdf)
- L-10: Complex Pipelining: Superscalar and Scoreboarding (pdf | split pdf)
- L-11: Out of Order Execution and Register Renaming (pdf | split pdf)
- L-12: Branch Prediction (pdf)
- L-13: Speculative Execution and Recovery (pdf | split pdf)
- L-14: Advanced Memory Operations (pdf)
- L-15: Multithreading (pdf)
- L-16: VLIW (pdf)
- L-17: Vector Processors (pdf)
- L-18: GPU Architectures (pdf)
- L-19: Reliability (pdf)
- L-20: On-chip Networking (I) (pdf)
- L-21: On-chip Networking (II) (pdf)
- L-22: Cache Coherence (I) (pdf)
- L-23: Cache Coherence (II) (pdf)
- L-24: Relaxed Memory Models (pdf)
- L-25: Transactional Memory (pdf)
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