Most of the documents referenced by this page are available in PDF format. On Athena, Mozilla is already configured with the necessary plug-in to view PDF files. To configure the browser on your machine you may need to download and install the Adobe Acrobat Reader.
These slides are made available for the convenience of our students. Others may use them for noncommercial purposes as long as MIT and the original authors are appropriately credited.
- L01: Overview [ PDF | 4UP ]
- L02: Verilog 1 - Fundamentals [ PDF | 4UP ]
- L03: Verilog 2 - Design Examples [ PDF | 4UP ]
- L04: CMOS Transistors, Gates, and Wires [ PDF | 4UP ]
- L05: Standard-Cell ASICs: Synthesis, Placement, and Routing [ PDF | 4UP ]
- L06: Handling Physical Design Issues in ASIC Toolflows [ PDF | 4UP ]
- L07: Bluespec 1 - Motivation [ PDF | 4UP ]
- L08: Bluespec 2 - Types [ PDF | 4UP ]
- L09: Bluespec 3 - 802.11a Example [ PDF | 4UP ]
- L10: Bluespec 4 - Rule Scheduling and Synthesis [ PDF | 4UP ]
- L11: Bluespec 5 - Rule Scheduling [ PDF | 4UP ]
- L12: Bluespec 6 - Processors [ PDF | 4UP ]
- L13: Bluespec 7 - Language Semantics [ PDF | 4UP ]
- L14: Bluespec 8 - Modules and Interfaces [ PDF | 4UP ]
There will be one 90 minute quiz on Friday, March 24 in class. The quiz is closed book.
See the schedule for due dates and the course information for class policies on turning in labs and collaboration. The SMIPS Processor Specification contains details on the SMIPS ISA which is used in several of the labs.
- Lab 1: Verilog RTL for 2-Stage SMIPSv2 Processor [ PDF ]
- Lab 2: ASIC Implementation for 2-Stage SMIPSv2 Processor [ PDF ]
- Lab 3: Bluespec and ASIC Implementation for 4-Stage SMIPSv2 Processor [ PDF ]
The following tutorials show how to use the 6.375 toolflow on Athena/Linux. See 6.375 Athena Computing Resources for more information on the computing resources available for the class.
- T01: Simulating Verilog RTL Using Synopsys VCS [ PDF ]
- T02: Using CVS to Manage Source RTL [ PDF ]
- T03: Assembly Programming for the SMIPS Processor
- T04: RTL-to-Gates Synthesis using Synopsys Design Compiler [ PDF ]
- T05: Automatic Placement and Routing using Cadence Encounter [ PDF ]
- T06: Power Analysis using Synopsys VCS and Cadence Encounter
- T07: Generating On-Chip SRAMs using RapidCompile
- T08: GAA-to-RTL Synthesis using the Bluespec Compiler [ PDF ]